a. Field of Invention
The present invention relates generally to the electrostatic discharge (ESD) protection of integrated circuits, and more particularly, to providing protection during ESD testing of integrated circuits.
b. Background of Invention
An electrostatic discharge (ESD) event may cause spurious or unwanted current spikes to flow through an integrated circuit. As a result, one or more devices within the integrated circuit may become damaged based on electrostatically discharged high current values (e.g., 1-10 A) causing dielectric (e.g., gate oxide breakdown) and/or metal (e.g., wire burn out) failure. As integrated circuit devices shrink in size, they may become more susceptible to ESD damage.
Integrated circuit manufacturers or other entities may engage in ESD testing in order to determine how resilient their integrated circuit devices are to ESD discharge events. Accordingly, it may be advantageous to protect the various devices within an integrated circuit during the ESD testing process.